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Data Sheet, Rev. 1.0, Sep. 2004
HYS64T16000HU-[3.7/5]-A HYS72T32000HU-[3.7/5]-A HYS64T32001HU-[3.7/5]-A
240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM UDIMM SDRAM RoHS Compliant
Memory Products
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The information in this document is subject to change without notice. Edition 2004-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.0, Sep. 2004
HYS64T16000HU-[3.7/5]-A HYS72T32000HU-[3.7/5]-A HYS64T32001HU-[3.7/5]-A
240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM UDIMM SDRAM RoHS Compliant
Memory Products
Never
stop
thinking.
HYS64T16000HU-[3.7/5]-A, HYS72T32000HU-[3.7/5]-A, HYS64T32001HU-[3.7/5]-A Revision History: Previous Revision: Page All Rev. 1.0 Rev. 0.22 2004-09 2004-04
Subjects (major changes since last revision) All Product Types replaced by HU-products (RoHS Compliant products)
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Table of Contents 1 1.1 1.2 2 2.1 2.1.1 2.1.2 2.1.3 3 3.1 3.2 4 4.1 5 6 6.1 6.2 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Raw Card A x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Raw Card A x72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Raw Card C x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 24 ODT (On Die Termination) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Raw Card C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Raw Card A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
240-Pin Unbuffered DDR2 SDRAM Modules DDR2 SDRAM
HYS64T16000HU-[3.7/5]-A HYS72T32000HU-[3.7/5]-A HYS64T32001HU-[3.7/5]-A
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
*
Features
* * * * * * * * Programmable CAS Latencies (3, 4 and 5), Burst Length (8 & 4) and Burst Type Burst Refresh, Distributed Refresh and Self Refresh All inputs and outputs SSTL_1.8 compatible OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Serial Presence Detect with E2PROM UDIMM Dimensions (nominal): 30 mm high, 133.35 mm wide Based on JEDEC standard reference layouts Raw Card "A" and "C" RoHS Compliant Products1)
* * *
240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. 16M x 64, 32M x 64, 32M x 72 module organization, and 16M x 16, 32M x 8 chip organization JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 256 Mb DDR2 SDRAMs in P-TFBGA-84 and P-TFBGA-60 chipsize packages Performance -3.7
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-5 PC2-3200 3-3-3 200 200 200 15 15 40 55
Units -- MHz MHz MHz ns ns ns ns
PC2-4200 4-4-4
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Overview
1.2
Description
The memory array is designed with 256Mb DoubleData-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The INFINEON HYS[64/72]T[16/32][000/001]HU- [3.7/5]-A module family are unbuffered DIMM modules "UDIMMs" with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 16M x 64 (128MB), 32M x 64 (256MB), and as ECC modules in 32M x 72 (256MB) organization and density, intended for mounting into 240-pin connector sockets. Table 2
Ordering Information for RoHS Compliant Products Compliance Code2) Description SDRAM Technology
Product Type1) PC2-3200
HYS64T16000HU-3.7-A 128MB 1Rx16 PC2-4200U-444-11-C1 1 Rank, Non-ECC 256 Mbit (x16)3) HYS64T32001HU-3.7-A 256MB 1Rx8 PC2-4200U-444-11-A1 HYS72T32000HU-3.7-A 256MB 1Rx8 PC2-4200E-444-11-A1 PC2-4200 HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A 128MB 1Rx16 PC2-3200U-333-11-C1 1 Rank, Non-ECC 256 Mbit (x16) 256MB 1Rx8 PC2-3200U-333-11-A1 256MB 1Rx8 PC2-3200E-333-11-A1 1 Rank, Non-ECC 256 Mbit (x8) 1 Rank, ECC 256 Mbit (x8) 1 Rank, Non-ECC 256 Mbit (x8) 1 Rank, ECC 256 Mbit (x8)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T16000HU-5-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 7 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200U-444-11- C1", where 4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "C". 3) Only on request
Table 3 DIMM Density 128 MByte 256 MByte Table 4
Address Format Module Organization 16M x 64 32M x 72 Memory Ranks 1 1 ECC/ Non-ECC Non-ECC ECC # of SDRAMs 4 9 # of row/bank/column Raw bits Card 13/2/9 13/2/10 C A
Components on Modules 1) DRAM Components2) HYB18T256160AF-3.7 HYB18T256800AF-3.7 HYB18T256800AF-3.7 HYB18T256160AF-5 HYB18T256800AF-5 HYB18T256800AF-5 DRAM Density 256 Mbit 256 Mbit 256 Mbit 256 Mbit 256 Mbit 256 Mbit DRAM Organisation 16M x 16 32M x 8 32M x 8 16M x 16 32M x 8 32M x 8
Product Type2) HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A
2) Green Product
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Data Sheet
7
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules (x64) and Figure 2 for ECC modules (x72). Table 5 Pin# Clock Signals 185 137 220 186 138 221 52 171 CK0 CK1 CK2 CK0 CK1 CK2 CKE0 CKE1 I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Clock Enable Rank 1:0 Note: Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE LOW initiates the Power Down Mode or the Self Refresh Mode. Note: 2 Ranks module NC Control Signals 193 76 S0 S1 I I SSTL SSTL Chip Select Rank 1:0 Note: Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical banks". Note: 2 Ranks module NC 192 RAS NC I -- SSTL Note: 1 Rank module Row Address Strobe Note: When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. 74 73 Address Signals 71 190 54 BA0 BA1 BA2 NC I I I NC SSTL SSTL SSTL -- Bank Address Bus 1:0 Note: Selects which DDR2 SDRAM internal bank of four or eight is activated. Bank Address Bus 2 Note: Greater than 512Mb DDR2 SDRAMS Note: Less than 1Gb DDR2 SDRAMS CAS WE I I SSTL SSTL Column Address Strobe Write Enable NC -- Note: 1 Rank module Clock Signals 2:0, Complement Clock Signals 2:0 Note: The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Pin Configuration of UDIMM Name Pin Buffer Function Type Type
Data Sheet
8
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 188 183 63 182 61 60 180 58 179 177 70 57 176 196 Pin Configuration of UDIMM (cont'd) Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC Pin Buffer Function Type Type I I I I I I I I I I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- Address Signal 13 Note: 1 Gbit based module and 512M x4/x8 Note: 1. Module based on 1 Gbit x16 2. Module based on 512 Mbit x16 or smaller 174 A14 NC Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Note: Data Input/Output pins I NC SSTL -- Address Signal 14 Note: Modules based on 2 Gbit Note: Modules based on 1 Gbit or smaller Address Bus 12:0 Note: During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is LOW, then BA0-BAn are used to define which bank to precharge.
Data Sheet
9
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 Data Sheet Pin Configuration of UDIMM (cont'd) Name DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 10 Rev. 1.0, 2004-09 02182004-DHQB-4RRW Data Bus 63:0
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# 111 116 117 229 230 235 236 Check Bit Signal 42 CB0 NC 43 CB1 NC 48 CB2 NC 49 CB3 NC 161 CB4 NC 162 CB5 NC 167 CB6 NC 168 CB7 NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- Check Bit 0 Note: ECC type module only Note: Non-ECC module Check Bit 1 Note: ECC type module only Note: Non-ECC module Check Bit 2 Note: ECC type module only Note: Non-ECC module Check Bit 3 Note: ECC type module only Note: Non-ECC module Check Bit 4 Note: ECC type module only Note: Non-ECC module Check Bit 5 Note: ECC type module only Note: Non-ECC module Check Bit 6 Note: ECC type module only Note: Non-ECC module Check Bit 7 Note: ECC type module only Note: Non-ECC module Pin Configuration of UDIMM (cont'd) Name DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0
Data Sheet
11
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# Data Strobe Bus 7 16 28 37 84 93 105 114 46 6 15 27 36 83 92 104 113 45 125 134 146 155 202 211 223 232 164 EEPROM 120 SCL I CMOS Serial Bus Clock Note: This signal is used to clock data into and out of the SPD EEPROM. 119 SDA I/O OD Serial Bus Data Note: This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to to VDDSPD on the motherboard to act as a pull-up. 239 240 101 Data Sheet SA0 SA1 SA2 I I I CMOS Serial Address Select Bus 2:0 CMOS Note: Address pins used to select the Serial Presence Detect base address. CMOS 12 Rev. 1.0, 2004-09 02182004-DHQB-4RRW DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask Bus 8:0 Note: The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. Note: See block diagram for corresponding DQ M signals Data Strobe Bus 8:0 Note: The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. Note: See block diagram for corresponding DQ signals Complement Data Strobe Bus 8:0 Note: See block diagram for corresponding DQ signals Pin Configuration of UDIMM (cont'd) Name Pin Buffer Function Type Type
Data Mask Signals
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 5 Pin# Power Supplies 1 238 Pin Configuration of UDIMM (cont'd) Name Pin Buffer Function Type Type AI -- I/O Reference Voltage Note: Reference voltage for the SSTL-18 inputs. EEPROM Power Supply Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module. 51,56,62,72,75, 78,170,175,181, 191,194
VREF
VDDSPD PWR --
VDDQ
PWR --
I/O Driver Power Supply
VDD 53,59,64,67,69, 172,178,184,187, 189,197
2,5,8,11,14,17, VSS 20,23,26,29,32, 35,38,41,44,47, 50,65,66,79,82, 85,88,91,94,97, 100,103,106, 109,112,115,118, 121,124,127, 130,133,136,139, 142,145,148, 151,154,157,160, 163,166,169, 198,201,204,207, 210,213,216, 219,222,225,228, 231,234,237 Other Pins 195 77 ODT0 ODT1
PWR --
Power Supply Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
GND --
Ground Plane Note: Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
I I
SSTL SSTL
On-Die Termination Control 0 On-Die Termination Control 1 Note: Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2 Rank modules
NC 18,19,55,68,102, NC 126,135,147, 156,165,173,203, 212, 224,233 Table 6 I O I/O Data Sheet
NC NC
-- --
Note: 1 Rank modules Not connected Note: Pins not connected on Infineon UDIMMs
Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. 13 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Abbreviation
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration Table 6 AI PWR GND NC Table 7 SSTL LV-CMOS CMOS OD Abbreviations for Pin Type (cont'd) Description Input. Analog levels. Power Ground Not Connected Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation
Abbreviation
Data Sheet
14
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
VREF - Pin 001 DQ0 V SS DQ2 V SS DQ9 - Pin 003 - Pin 005 - Pin 009 - Pin 011 - Pin 013
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 NC V SS DQ11 DQ16 V SS DQS2 DQ18 V SS DQ25 DQS3 V SS DQ27 NC V SS NC NC V SS
- Pin 002 - Pin 004 - Pin 006 - Pin 008 - Pin 010 - Pin 012 - Pin 014 - Pin 016 - Pin 018 - Pin 020 - Pin 022 - Pin 024
Pin 122 - DQ4 Pin 124 - V SS Pin 126 - NC Pin 128 - DQ6 Pin 130 - V SS Pin 132 - DQ13 Pin 134 - DM1 Pin 136 - V SS Pin 138 - CK1 Pin 140 - DQ14 Pin 142 - V SS Pin 144 - DQ21
Pin 121 - V SS Pin 123 - DQ5 Pin 125 - DM0 Pin 127 - V SS Pin 129 - DQ7 Pin 131 - DQ12 Pin 133 - V SS Pin 135 - NC Pin 137 - CK1 Pin 139 - V SS Pin 141 - DQ15 Pin 143 - DQ20 Pin 145 - V SS Pin 147 - NC Pin 149 - DQ22 Pin 151 - V SS Pin 153 - DQ29 Pin 155 - DM3 Pin 157 - V SS Pin 159 - DQ31 Pin 161 - NC Pin 163 - V SS Pin 165 - NC Pin 167 - NC Pin 169 - V SS Pin 171 - CKE1 Pin 173 - NC Pin 175 - V DDQ Pin 177 - A9 Pin 179 - A8 Pin 181 - V DDQ Pin 183 - A1
DQS0 - Pin 007
DQS1 - Pin 015 V SS - Pin 017 NC - Pin 019 DQ10 - Pin 021 - Pin 023 V
SS
DQ17 - Pin 025 DQS2 - Pin 027 V SS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 V SS - Pin 035 DQS3 - Pin 037 DQ26 - Pin 039 V SS NC NC V SS NC V DD NC A11 V DD A4 A2 - Pin 041 - Pin 043 - Pin 045 - Pin 047 - Pin 049 - Pin 053 - Pin 055 - Pin 057 - Pin 059 - Pin 061 - Pin 063
FRONTSIDE
- Pin 030 - Pin 032 - Pin 034 - Pin 036 - Pin 038 - Pin 040 - Pin 042 - Pin 044 - Pin 046 - Pin 048 - Pin 050
BACKSIDE
- Pin 026 - Pin 028
Pin 146 - DM2 Pin 148 - V SS Pin 150 - DQ23 Pin 152 - DQ28 Pin 154 - V SS Pin 156 - NC Pin 158 - DQ30 Pin 160 - V SS Pin 162 - NC Pin 164 - NC Pin 166 - V SS Pin 168 - NC Pin 170 - V DDQ Pin 172 - V DD Pin 174 - A14 Pin 176 - A12 Pin 178 - V DD Pin 180 - A6 Pin 182 - A3 Pin 184 - V DD
V DDQ - Pin 051
CKE0 - Pin 052 NC/BA2 - Pin 054 - Pin 056 V DDQ A7 A5 V DDQ V DD - Pin 058 - Pin 060 - Pin 062 - Pin 064
V SS V DD V DD BA0 WE
- Pin 065 - Pin 067 - Pin 069 - Pin 071 - Pin 073
V SS
- Pin 066
NC - Pin 068 A10/AP - Pin 070 - Pin 072 V
DDQ
Pin 186 - CK0 Pin 188 - A0 Pin 190 - BA1 Pin 192 - RAS Pin 194 - V DDQ Pin 196 - NC/A13 Pin 198 - V SS Pin 200 - DQ37 Pin 202 - DM4 Pin 204 - V SS Pin 206 - DQ39 Pin 208 - DQ44 Pin 210 - V SS Pin 212 - NC Pin 214 - DQ46 Pin 216 - V SS Pin 218 - DQ53 Pin 220 - CK2 Pin 222 - V SS Pin 224 - NC Pin 226 - DQ54 Pin 228 - V SS Pin 230 - DQ61 Pin 232 - DM7 Pin 234 - V SS Pin 236 - DQ63 Pin 238 Pin 240 V DDSPD SA1
Pin 185 - CK0 Pin 187 - V DD Pin 189 - V DD Pin 191 - V DDQ Pin 193 - S0 Pin 195 - ODT0 Pin 197 - V DD Pin 199 - DQ36 Pin 201 - V SS Pin 203 - NC Pin 205 - DQ38 Pin 207 - V SS Pin 209 - DQ45 Pin 211 - DM5 Pin 213 - V SS Pin 215 - DQ47 Pin 217 - DQ52 Pin 219 - V SS Pin 221 - CK2 Pin 223 - DM6 Pin 225 - V SS Pin 227 - DQ55 Pin 229 - DQ60 Pin 231 - V SS Pin 233 - NC Pin 235 - DQ62 Pin 237 Pin 239 V SS SA0 MPPT0150
V DDQ - Pin 075 ODT1 - Pin 077 V SS - Pin 079 DQ33 - Pin 081 DQS4 - Pin 083 V SS - Pin 085 DQ35 - Pin 087 DQ40 - Pin 089 V SS - Pin 091 DQS5 - Pin 093 DQ42 - Pin 095 V SS - Pin 097 DQ49 - Pin 099 SA2 - Pin 101 V SS - Pin 103 DQS6 - Pin 105 DQ50 - Pin 107 V SS - Pin 109 DQ57 - Pin 111 DQS7 - Pin 113 V SS SDA - Pin 115 - Pin 119 DQ59 - Pin 117
CAS NC/S1 V DDQ DQ32 V SS DQS4 DQ34 V SS DQ41 DQS5 V SS DQ43 DQ48 V SS NC DQS6 V SS DQ51 DQ56 V SS DQS7 DQ58 V SS SCL
- Pin 074 - Pin 076 - Pin 078 - Pin 080 - Pin 082 - Pin 084 - Pin 086 - Pin 088 - Pin 090 - Pin 092 - Pin 094 - Pin 096 - Pin 098 - Pin 100 - Pin 102 - Pin 104 - Pin 106 - Pin 108 - Pin 110 - Pin 112 - Pin 114 - Pin 116 - Pin 118 - Pin 120
Figure 1
Pin Configuration UDIMM x64 (240 Pin)
Data Sheet
15
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
VREF - Pin 001 DQ0 V SS DQ2 V SS DQ9 - Pin 003 - Pin 005 - Pin 009 - Pin 011 - Pin 013
V SS DQ1 DQS0 V SS DQ3 DQ8 V SS DQS1 NC V SS DQ11 DQ16 V SS DQS2 V SS V SS DQ25 DQS3 V SS DQ27 CB0 V SS DQS8 CB2 V SS CKE0
- Pin 002 - Pin 004 - Pin 006 - Pin 008 - Pin 010 - Pin 012 - Pin 014 - Pin 016 - Pin 018 - Pin 020 - Pin 022 - Pin 024
Pin 122 - DQ4 Pin 124 - V SS Pin 126 - NC Pin 128 - DQ6 Pin 130 - V SS Pin 132 - DQ13 Pin 134 - DM1 Pin 136 - NC Pin 138 - CK1 Pin 140 - DQ14 Pin 142 - V SS Pin 144 - DQ21 Pin 146 - DM2
Pin 121 - V SS Pin 123 - DQ5 Pin 125 - DM0 Pin 127 - V SS Pin 129 - DQ7 Pin 131 - DQ12 Pin 133 - V SS Pin 135 - NC Pin 137 - CK1 Pin 139 - V SS Pin 141 - DQ15 Pin 143 - DQ20 Pin 145 - V SS Pin 147 - NC Pin 149 - DQ22 Pin 151 - V SS Pin 153 - DQ29 Pin 155 - DM3 Pin 157 - V SS Pin 159 - DQ31 Pin 161 - CB4 Pin 163 - V SS Pin 165 - NC Pin 167 - CB6 Pin 169 - V SS Pin 171 - CKE1 Pin 173 - NC Pin 175 - V DDQ Pin 177 - A9 Pin 179 - A8 Pin 181 - V DDQ Pin 183 - A1
DQS0 - Pin 007
DQS1 - Pin 015 V SS - Pin 017 NC - Pin 019 DQ10 - Pin 021 - Pin 023 V SS DQ17 - Pin 025 DQS2 - Pin 027 V SS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 V SS - Pin 035 DQS3 - Pin 037 DQ26 - Pin 039 V SS CB1 - Pin 041 - Pin 043
FRONTSIDE
- Pin 030 - Pin 032 - Pin 034 - Pin 036 - Pin 038 - Pin 040 - Pin 042 - Pin 044 - Pin 046 - Pin 048 - Pin 050
BACKSIDE
- Pin 026 - Pin 028
Pin 148 - V SS Pin 150 - DQ23 Pin 152 - DQ28 Pin 154 - V SS Pin 156 - NC Pin 158 - DQ30 Pin 160 - V SS Pin 162 - CB5 Pin 164 - DM8 Pin 166 - V SS Pin 168 - CB7 Pin 170 - V DDQ Pin 172 - V DD Pin 174 - A14 Pin 176 - A12 Pin 178 - V DD Pin 180 - A6 Pin 182 - A3 Pin 184 - V DD
DQS8 - Pin 045 V SS - Pin 047 CB3 V DD NC A11 V DD A4 A2 - Pin 049 - Pin 053 - Pin 055 - Pin 057 - Pin 059 - Pin 061 - Pin 063 V DDQ - Pin 051
- Pin 052 NC/BA2 - Pin 054 - Pin 056 V DDQ A7 A5 V DDQ V DD - Pin 058 - Pin 060 - Pin 062 - Pin 064
V SS V DD V DD BA0 WE
- Pin 065 - Pin 067 - Pin 069 - Pin 071 - Pin 073
V SS
- Pin 066
NC - Pin 068 A10/AP - Pin 070 - Pin 072 V
DDQ
Pin 186 - CK0 Pin 188 - A0 Pin 190 - BA1 Pin 192 - RAS Pin 194 - V DDQ Pin 196 - NC/A13 Pin 198 - V SS Pin 200 - DQ37 Pin 202 - DM4 Pin 204 - V SS Pin 206 - DQ39 Pin 208 - DQ44 Pin 210 - V SS Pin 212 - NC Pin 214 - DQ46 Pin 216 - V SS Pin 218 - DQ53 Pin 220 - CK2 Pin 222 - V SS Pin 224 - NC Pin 226 - DQ54 Pin 228 - V SS Pin 230 - DQ61 Pin 232 - DM7 Pin 234 - V SS Pin 236 - DQ63 Pin 238 Pin 240 V DDSPD SA1
Pin 185 - CK0 Pin 187 - V DD Pin 189 - V DD Pin 191 - V DDQ Pin 193 - S0 Pin 195 - ODT0 Pin 197 - V DD Pin 199 - DQ36 Pin 201 - V SS Pin 203 - NC Pin 205 - DQ38 Pin 207 - V SS Pin 209 - DQ45 Pin 211 - DM5 Pin 213 - V SS Pin 215 - DQ47 Pin 217 - DQ52 Pin 219 - V SS Pin 221 - CK2 Pin 223 - DM6 Pin 225 - V SS Pin 227 - DQ55 Pin 229 - DQ60 Pin 231 - V SS Pin 233 - NC Pin 235 - DQ62 Pin 237 Pin 239 V SS SA0 MPPT0160
V DDQ - Pin 075 ODT1 - Pin 077 V SS - Pin 079 DQ33 - Pin 081 DQS4 - Pin 083 V SS - Pin 085 DQ35 - Pin 087 DQ40 - Pin 089 V SS V SS V SS - Pin 091 - Pin 095 - Pin 097 DQS5 - Pin 093
CAS NC/S1 V DDQ DQ32 V SS DQS4 DQ34 V SS DQ41 DQS5 V SS DQ43 DQ48 V SS NC DQS6 V SS DQ51 DQ56 V SS DQS7 DQ58 V SS SCL
- Pin 074 - Pin 076 - Pin 078 - Pin 080 - Pin 082 - Pin 084 - Pin 086 - Pin 088 - Pin 090 - Pin 092 - Pin 094 - Pin 096 - Pin 098 - Pin 100 - Pin 102 - Pin 104 - Pin 106 - Pin 108 - Pin 110 - Pin 112 - Pin 114 - Pin 116 - Pin 118 - Pin 120
DQ49 - Pin 099 SA2 - Pin 101 V SS - Pin 103 DQS6 - Pin 105 DQ50 - Pin 107 V SS - Pin 109 DQ57 - Pin 111 DQS7 - Pin 113 V SS SDA - Pin 115 - Pin 119 DQ59 - Pin 117
Figure 2
Pin Configuration UDIMM x72 (240 Pin)
Data Sheet
16
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
2.1
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
Block Diagrams
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' 966 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 9''63' 9''9''4 95() 966 9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
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03%7
Figure 3 Notes 1. 2. 3. 4.
Block Diagram Raw Card A UDIMM (x64, 1 Rank, x8)
DQ,DQS,DQS,DM resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 5.1 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 8 Clock Input CK0,CK0 CK1,CK1 CK2,CK3
Clock Signal Loads SDRAMs 2 3 3 Note
Data Sheet
17
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' 9''63' &$6 6'5$0V ' ' :( 6'5$0V ' ' 9''9''4 &.( 6'5$0V ' ' 95() 2'7 6'5$0V ' ' 966 966 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4
6&/ 6'$ 6$ 9'' 63' ((3520 ( 6$ 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' ' '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ' '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 '4 '4 '4 '4 '4 '4 '4 '4 '0 '46 '46 &% &% &% &% &% &% &% &%
6&/ 6'$ $ $ $ :3 9VV '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 '0 &6 '46 '46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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03%7
Figure 4 Notes 1. 2. 3. 4.
Block Diagram Raw Card A UDIMM (x72, 1 Rank, x8)
DQ,DQS,DQS,DM,CB resistors are 22 5 % BAn, An, RAS, CAS, WE resistors are 5.1 5 % ODT,CKE,S capacitors are 24 pF All CK lines have resistor termination between CK an CK.
Table 9 Clock Input CK0,CK0 CK1,CK1 CK2,CK3
Clock Signal Loads SDRAMs 3 3 3 Note
1)
1) 2 SDRAMS for CK0 in case of non-ECC
Data Sheet
18
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Pin Configuration
%$ %$ $ $Q 5$6 &$6 :( &.( 2'7 6 6&/ 6'$ 6$ 6$
966 6&/ 6'$ $ $ $ :3
%$ %$ 6'5$0V ' ' $ $Q 6'5$0V ' ' 5$6 6'5$0V ' ' &$6 6'5$0V ' ' :( 6'5$0V ' ' &.( 6'5$0V ' ' 2'7 6'5$0V ' ' (
9''63' 9''9''4 95() 966
9'' 63' ((3520 ( 9''9''4 6'5$0V ' ' 95() 6'5$0V ' ' 966 6'5$0V ' '
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/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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/'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 /'0 &6 /'46 /'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 8'0 8'46 8'46 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2
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03%7
Figure 5 Notes
Block Diagram Raw Card C UDIMM (x64, 1Rank, x16)
1. DQ, DQS, DM resistors are 22 5 % 2. BAn, An, RAS, CAS, WE resistors are 10 5 %
Data Sheet
19
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
3
Table 10 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions 1)2)3)4)5)6)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
IDD3P(0) IDD3P(1) IDD4R
Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
20
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions Table 10 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max.
IDD Measurement Conditions (cont'd)1)2)3)4)5)6)
Symbol
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD: LOW is defined as VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
STABLE is defined as: inputs are stable at a HIGH or LOW level FLOATING is defined as: inputs are VREF = VDDQ /2 SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) For details and notes see the relevant INFINEON component data sheet
Data Sheet
21
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
Table 11
IDD Specification for HYS[64/72]T[16/32][000/001]HU-3.7-A
HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A Unit Notes
Product Type
Organization
128 MB x64 1 Rank -3.7
256 MB x64 1 Rank -3.7 Max. 440 480 -- 280 30 200 130 30 280 560 -- 680 -- 680 50 30 1080 --
256 MB x72 1 Rank -3.7 Max. 500 540 -- 320 40 230 140 40 320 630 -- 770 -- 770 50 40 1220 -- mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x8x161) x81) x16 x8x161) x8x161) x8x161) x8x161) x8x161) x8x161) x81) x16 x81) x16 x8x161) x8x161) x8x161) x81) x16
Symbol
Max. 220 -- 240 140 20 100 60 20 140 -- 320 -- 400 340 20 20 -- 600
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3P(MRS= 0) IDD3P(MRS= 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Data Sheet
22
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
Table 12
IDD Specification for HYS[64/72]T[16/32][000/001]HU-5-A
HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A Unit Notes
Product Type
Organization
128 MB x64 1 Rank -5
256 MB x64 1 Rank -5 Max. 400 -- 440 -- 220 30 160 100 30 240 480 -- 560 -- 640 50 30 1000 --
256 MB x72 1 Rank -5 Max. 450 -- 500 -- 250 40 180 120 40 270 540 -- 630 -- 720 50 40 1130 -- mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x81) x16 x81) x16 x8x161) x8x161) x8x161) x8x161) x8x161) x8x161) x81) x16 x8 x161) x8x161) x8x161) x8x161) x81) x16
Symbol
Max. -- 200 -- 220 110 20 80 50 20 120 -- 280 -- 360 320 20 20 -- 560
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3P(MRS= 0) IDD3P(MRS= 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Data Sheet
23
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
IDD Specifications and Conditions
3.1
IDD Test Conditions
IDD Measurement Test Conditions
Symbol -3.7 4 3.75 15 60 7.5 10 45 70000 15 75 7.8 -5 3 5 15 55 7.5 10 40 70000 15 75 7.8 Unit PC2-4200-4-4-4 PC2-3200-3-3-3
For testing the IDD parameters, the timing parameters as in Table 11 are used. Table 13 Parameter CAS Latency
CL(IDD) Clock Cycle Time tCK(IDD) Active to Read or Write delay tRCD(IDD) Active to Active / Auto-Refresh command period tRC(IDD) 1) Active bank A to Active bank B command delay x8 tRRD(IDD) 2) x16 tRRD(IDD) Active to Precharge Command tRAS.MIN(IDD) Active to Precharge Command tRAS.MAX(IDD) Precharge Command Period tRP(IDD) Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Average periodic Refresh interval tREFI
1) For modules based on x8 components 2) For modules based on x16 components
tCK
ns ns ns ns ns ns ns ns ns s
3.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 14 Parameter ODT current per terminated pin
Symbol Min. 5 2.5 10 5
Typ. 6 3 12 6
Max. Unit 7.5 3.75 15 7.5
EMRS(1) State
Enabled ODT current per DQ IODTO ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0
IODTT
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
24
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics
4
4.1
Table 13 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values Min. Max. 2.3 2.3 2.3 95 V V V % - 0.5 - 1.0 - 0.5 5 Unit Note/Test Condition
1) 1) 1) 1)
VIN, VOUT Voltage on VDD relative to VSS VDD Voltage on VDDQ relative to VSS VDDQ Storage Humidity (without condensation) HSTG
Voltage on any pins relative to VSS
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Table 14 Parameter
Operating Conditions Symbol Values Min. Max. +65 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
HOPR
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. 2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported 3) Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s 4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C Case Temperature before initiating Self-Refresh operation. 5) Up to 3000 m.
Table 15 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) Values Min. Nom. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5 V V V V V V A
3) 1) 2)
Unit
Notes
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5
IL
1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Data Sheet
25
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics Table 16 Speed Grade Definition Speed Bins DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 RAS-CAS-Delay Row Precharge Time Row Active Time Row Cycle Time Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until recognized as low. 5)
VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
4) The output timing reference voltage level is VTT.
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Max. +500 -- 0.55 -- 0.55 -- -- -500 2 0.45 3 0.45 WR + tRP -5 DDR2-400 3-3-3 Min. -600 2 0.45 3 0.45 WR + tRP Max. +600 -- 0.55 -- 0.55 -- -- ps Unit Notes1)
Table 17 Parameter
DQ output access time from CK / CK CK, CK high-level width width
tAC
CAS A to CAS B command period tCCD
tCH CKE minimum high and low pulse tCKE
CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe)
tCK tCK tCK tCK tCK
ns
tCL tDAL tDELAY
tIS + tCK + tIH
tIS + tCK + tIH
275 25 0.35 -500
tDH(base) 225
-- -- -- +450
-- -- -- +500
ps ps
DQ and DM input hold time (single tDH1(base) -25 ended data strobe) DQ and DM input pulse width (each tDIPW input) DQS output access time from CK / tDQSCK CK 0.35 -450
tCK
ps
Data Sheet
26
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont'd) Symbol -3.7 DDR2-533 4-4-4 Min. DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) Max. -- 300 0.35 -- WL - 0.25 -5 DDR2-400 3-3-3 Min. 0.35 -- Max. -- 350 Unit Notes1)
tDQSL,H tDQSQ tDQSS
tCK
ps
WL + 0.25 WL - 0.25 -- -- -- -- 150 25 0.2 0.2
WL + 0.25 tCK -- -- -- -- ps ps
tDS(base) 100 tDS1(base) -25 tDSH
0.2 0.2
tCK tCK
DQS falling edge to CK setup time tDSS (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input pulse width (each input) Address and control input setup time
tHP tHZ
MIN. (tCL, tCH) -- 375 0.6
MIN. (tCL, tCH) -- 475 0.6
tAC.MAX
-- --
tAC.MAX
-- --
ps ps
Address and control input hold time tIH(base)
tIPW tIS(base)
tCK
ps ps ps
250 2 x tAC.MIN
--
350 2 x tAC.MIN
--
DQ low-impedance time from CK / tLZ(DQ) CK DQS low-impedance from CK / CK tLZ(DQS) Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/AutoRefresh command period
tAC.MAX tAC.MAX
-- 12 -- 400 7.8 3.9 -- -- 1.1 0.60 -- -- --
tAC.MAX tAC.MAX
-- 12 450 7.8 3.9 -- -- 1.1 0.60 -- -- --
tAC.MIN
2 0
tAC.MIN
2 0 -- -- -- 75
tMRD tOIT tQH tQHS tREFI tRFC
tCK
ns ps s s ns ns
2) 3)
tHP - tQHS
-- -- -- 75
tHPQ - tQHS --
Precharge-All (4 banks) command tRP period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Data Sheet
tRP + 1tCK
0.9 0.40 7.5 10 7.5
tRP + 1tCK
0.9 0.40 7.5 10 7.5
tRPRE tRPST tRRD tRTP
tCK tCK
ns ns ns
27
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Electrical Characteristics Table 17 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont'd) Symbol -3.7 DDR2-533 4-4-4 Min. Write preamble Write postamble Write recovery time for write without Auto-Precharge Write recovery time for write with Auto-Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Max. -- 0.60 -- 0.35xtCK 0.40 15 -5 DDR2-400 3-3-3 Min. 0.35xtCK 0.40 15 Max. -- 0.60 -- Unit Notes1)
tWPRE tWPST tWR
WR
tCK tCK
ns
tWR/tCK
7.5 2 -- --
tWR/tCK
10 2 -- --
tCK
ns
tWTR tXARD tXARDS
tCK tCK tCK
ns
6 - AL
--
6 - AL
--
Exit precharge power-down to any tXP valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
2) 0 TCASE 85 C 3) 85 C < TCASE 95 C
2
--
2
--
tXSNR tXSRD
tRFC +10
200
-- --
tRFC +10
200
-- --
tCK
1) For details and notes see the relevant INFINEON component data sheet
Table 18 Symbol
ODT AC Electrical Characteristics and Operating Conditions Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Notes
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
2) 1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5
2.5 tCK tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
28
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes
5
Table 21
SPD Codes
SPD Codes for HYS[64/72]T[16/32][000/001]HU-3.7-A HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0D 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 02 00 01 3D 50 50 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 3D 50 00 82 08 00 00 0C 04 38 00 02 00 01 3D 50 50
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200U-444 Rev. 1.1 HEX 80 08 08 0D 09 60 40 00 05 3D 50 00 82 10 00 00 0C 04 38 00 02 00 01 3D 50 50 29
PC2-4200U-444 PC2-4200U-444
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns]
Data Sheet
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS[64/72]T[16/32][000/001]HU-3.7-A (cont'd) HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 00 55 82 36 2B 21 1D Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 60 3C 1E 3C 2D 40 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 00 55 82 36 2B 21 1D
Label Code JEDEC SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Description
PC2-4200U-444 Rev. 1.1 HEX 60 3C 28 3C 2D 20 25 37 10 22 3C 1E 1E 00 00 3C 4B 80 1E 28 00 56 7A 32 29 1F 1B
PC2-4200U-444 PC2-4200U-444
tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N)
Data Sheet
30
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS[64/72]T[16/32][000/001]HU-3.7-A (cont'd) HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 28 14 2C 15 21 00 00 00 00 11 78 C1 00 xx 37 32 54 33 32 30 30 30 48 55 33 2E 37 41 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 28 14 2C 15 21 00 00 00 00 11 66 C1 00 xx 36 34 54 33 32 30 30 31 48 55 33 2E 37 41
Label Code JEDEC SPD Revision Byte# 53 54 55 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Description T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14
PC2-4200U-444 Rev. 1.1 HEX 25 13 2E 14 23 00 00 00 00 11 45 C1 00 xx 36 34 54 31 36 30 30 30 48 55 33 2E 37 41
PC2-4200U-444 PC2-4200U-444
Data Sheet
31
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 21 SPD Codes for HYS[64/72]T[16/32][000/001]HU-3.7-A (cont'd) HYS64T16000HU-3.7-A HYS64T32001HU-3.7-A HYS72T32000HU-3.7-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 20 20 20 20 1x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 20 20 20 20 1x xx xx xx xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 87 88 89 90 91 92 93 94 95 - 98 96 97 98 Description Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4)
PC2-4200U-444 Rev. 1.1 HEX 20 20 20 20 1x xx xx xx xx xx xx xx 00
PC2-4200U-444 PC2-4200U-444
99 - 127 Not used
Data Sheet
32
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes
Table 22
SPD Codes for HYS[64/72]T[16/32][000/001]HU-5-A HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0D 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 02 00 01 50 60 50 60 3C Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0D 0A 60 40 00 05 50 60 00 82 08 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200U-333 PC2-3200U-333 PC2-3200U-333 Rev. 1.1 HEX 80 08 08 0D 09 60 40 00 05 50 60 00 82 10 00 00 0C 04 38 00 02 00 01 50 60 50 60 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns]
Data Sheet
33
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS[64/72]T[16/32][000/001]HU-5-A (cont'd) HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 1E 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 00 53 82 2E 23 21 19 20 14 26 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 1E 3C 28 40 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 00 53 82 2E 23 21 19 20 14 26
Label Code JEDEC SPD Revision Byte# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Description
PC2-3200U-333 PC2-3200U-333 PC2-3200U-333 Rev. 1.1 HEX 28 3C 28 20 35 47 15 27 3C 28 1E 00 00 37 4B 80 23 2D 00 56 7A 2A 20 1F 17 1E 13 28 34
tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W)
Data Sheet
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS[64/72]T[16/32][000/001]HU-5-A (cont'd) HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 14 1F 00 00 00 00 11 CB C1 00 xx 37 32 54 33 32 30 30 30 48 55 35 41 20 20 20 20 20 20 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 14 1F 00 00 00 00 11 B9 C1 00 xx 36 34 54 33 32 30 30 31 48 55 35 41 20 20 20 20 20 20
Label Code JEDEC SPD Revision Byte# 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Description T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18
PC2-3200U-333 PC2-3200U-333 PC2-3200U-333 Rev. 1.1 HEX 13 20 00 00 00 00 11 99 C1 00 xx 36 34 54 31 36 30 30 30 48 55 35 41 20 20 20 20 20 20 35
Data Sheet
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
SPD Codes Table 22 SPD Codes for HYS[64/72]T[16/32][000/001]HU-5-A (cont'd) HYS64T16000HU-5-A HYS64T32001HU-5-A HYS72T32000HU-5-A 256 MB x72 1 Rank (x8) Rev. 1.1 HEX 1x xx xx xx xx 00 Rev. 1.0, 2004-09 02182004-DHQB-4RRW
Product Type
Organization
128 MB x64 1 Rank (x16)
256 MB x64 1 Rank (x8) Rev. 1.1 HEX 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 91 92 93 94 95 - 98 Description Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4)
PC2-3200U-333 PC2-3200U-333 PC2-3200U-333 Rev. 1.1 HEX 1x xx xx xx xx 00
99 - 127 Not used
Data Sheet
36
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Package Outlines
6
0.1 A B C
Package Outlines
133.35 128.95 2.7 MAX.
4
4x
1
4 2.5 5 63 55
120 C 0.4 1.27 0.1
A 1.5 0.1
3.8
121
240
2.3 0.1 10
30
(3)
Detail of contacts
0.2
1
0.8 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6
Package Outline Raw Card C L-DIM-240-3
Data Sheet
37
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
17.8
B
GLD09654
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Package Outlines
6.1
0.1 A B C
Raw Card A
133.35 128.95 0.1
0.3 C
1.27 0.1
4
1
4 0.1 2.5 0.1 5 0.1 63 0.1 55 0.1
120
30
2.7 MAX.
A 1.5 0.1
3.8
121
240 1) for ECC modules only 1)
10 0.1 17.8 0.1
2.3 0.1
B 3 MIN.
Detail of contacts
0.2
1
0.8 0.2
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
GLD09652
Figure 7
Package Outline L-DIM-240-1
Data Sheet
38
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
HYS[64/72]T[16/32][000/001]HU-[3.7/5]-A Unbuffered Double-Data-Rate-Two SDRAM Modules
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 23 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 24 and for components in Table 25. Table 23 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 24 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 25 1 2 3 4
DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533C DDR2-400B
Field Description INFINEON Component Prefix DRAM Technology
Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G
5 6 7 8 9
Raw Card Generation
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z D M R U
5+6 Number of I/Os
40 80 16
7 8 9
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
10 11
-3.7 -5
Data Sheet
39
Rev. 1.0, 2004-09 02182004-DHQB-4RRW
www.infineon.com
Published by Infineon Technologies AG

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